With the explosion of new application fields such as new energy vehicles, 5G, AI, etc., the demand for MOS tubes in motor-driven scenes has also surged, and domestic substitution has accelerated, which has put forward higher requirements for the technology and performance of MOS tubes. As one of the important discrete components, how are such tiny and precise electronic components produced? What high-tech processes are involved? Today, Heketai takes you into the microscopic world of MOS tubes.

Structure and principle of MOS tube

The full name of MOS tube is MOSFET, and its core structure includes semiconductor base, insulating layer, gate, source and drain, and parasitic diode. Through the coordination of electric field regulation and semiconductor characteristics, efficient power control and signal amplification can be realized. The semiconductor base (substrate) is use as a carrier, and aft that voltage is applied to the gate, the electric field below the insulating layer can form a conductive channel on the surface of the substrate; The source injects carriers, and the drain collects carrier conduction current. The polarity of the package is fixed by parasitic diodes, which simplifies the circuit design.

Manufacturing process flow of MOS tube

The manufacturing process of MOS tube is complex and precise, which mainly involves seven major processes, namely, substrate preparation, oxide layer formation, lithography and gate fabrication, source and drain doping, annealing, metallization and interconnection. According to the production content of different structures, the classification description is as follows.

1. Material selection: select high-purity monocrystalline silicon, and remove surface impurities by mechanical polishing and chemical cleaning.

2. Pretreatment: The silicon wafer from which impurities are removed needs to be annealed and oxidized to form an initial oxide layer to enhance the surface stability, such as silicon dioxide.

3. Thermal oxidation: The silicon wafer is placed in a high-temperature furnace, and oxygen and water vapor are introduced into it, so that a silicon dioxide insulation layer with a thickness of 20-300nm can be generated.

4. Chemical vapor deposition CVD: silicon dioxide is deposited on the surface of silicon through gaseous reactants, which can be used to form gate oxide or field oxide.

5. Polycrystalline silicon deposition: a polycrystalline silicon layer with a thickness of about 200-300nm is deposited on the insulating layer by CVD or PVD.

6, photoetching and etching: coating photoresist and exposing mask patterns, and retaining polysilicon in the gate region after development; Dry etching removes excess polysilicon to form a gate structure.

7. Ion implantation: define the window of source and drain regions by photolithography, and implant phosphorus (N-type) or boron (P-type) ions to form a low doping concentration region (LDD region), and anneal at high temperature (about 1000℃) to activate dopants and repair lattice damage.

8. High doping: conduct secondary ion implantation at the edge of source and drain regions to form regions with high doping concentration (such as N+ or P+) to reduce contact resistance.

Based on the above precision technology, Heketai has established a set of standardized and streamlined quality management system to ensure the quality of products in an all-round way, covering MOS products with multi-scenario application requirements. The following are MOS transistors selected by Heketai, which have significant advantages in key indicators such as on-resistance, switching speed and withstand voltage. The detailed parameters are as follows: